1. Field of the Invention
This invention relates to a semiconductor device having multiple conductive layers and more particularly to the connecting structure between one conductive layer and other conductive portions of the device. The present invention also relates to a method of manufacturing the semiconductor device.
2. Description of the Prior Art
In a semiconductor device, in particular in an intergrated circuit device, a multiple conductive-layer structure is used to form various portions of the device. In prior art devices connections to other conductive portions in this structure are achieved through contact holes simply formed by etching the insulation layers on the conductive portions to be connected. In this case, the thicknesses of the insulation layers on each conductive portion are not uniform and the number of the insulation layers differs at several portions of the device. Thus as a result of the etching process the thin portions of the device have larger holes than the thick portions because of too much side etching. In the large scale integrated circuit device (LSI), the influence of the peripheral pattern must be considered in forming the contact hole. Namely, when the contact hole is formed too large, it may cause short circuits with the peripheral conductive portions of the device or cause an increase in the coupling capacitance with the peripheral conductive portions. Thus this problem has produced many restrictions in the design of large scale integrated circuit devices.
The prior art process for forming contact holes will now be described with reference to the drawings. FIGS. 1 and 2 show the prior art process of forming the contact holes. A plurality of N.sup.+ type regions 2, 3, and 4 are formed in a P type semiconductor substrate 1. The N.sup.+ regions 2 and 3 are source and drain regions of an MOS transistor, respectively, and the N.sup.+ region 4 is a region of another MOS transistor or another circuit element. Each element formed by the N.sup.+ regions 2, 3, and 4 is separated by an element-separating layer 5 which is partially buried in the substrate 1. The separating layer 5 is made of SiO.sub.2 formed by a coplanar process. A gate electrode 7 is formed over the channel between the source region 2 and the drain region 3 through a gate insulation layer 6. This gate electrode 7 is made of polycrystalline silicon (poly-Si) and is simultaneously formed along with a conductive layer 8 on the separating layer 5. The gate electrode 7 and the conductive layer 8 are covered by a first insulation layer 9 made of SiO.sub.2. A contact hole is formed in the insulation layer 9. A source electrode 10', and a conductive layer 10 for connecting to another conductive layer are formed by using a photo-engraving process (PEP) and are made of poly-Si. It is natural that the other conductive layers are formed at other portions of the device at the same time. The conductive layer 10 forms the multiple conductive layer structure for the gate electrode 7 and the conductive layer 8. After the conductive layer 10 is formed, a second insulation layer 11 is formed. As shown in FIG. 2, contact hole 13 is to be formed in the second insulation layer 11, and contact holes 14 and 15 are to be formed through the first and second insulation layers 9, 11 by using a resist film 12 as a mask. In this case, the ultimate depth of the hole 13 will be t.sub.1 and that of the holes 14 and 15 will be t.sub.2 and t.sub.3 will be greater as shown in FIG. 1. The depths t.sub.2 and t.sub.3 than t.sub.1. Thus the hole 13 is formed first.
At the time shown in FIG. 2 the holes 14 and 15 do not yet reach the conductive layer 8 and the N.sup.+ region 4 as shown in FIG. 2. Therefore, the first insulation layer 9 must be etched further. The side etching of the hole 13 will be advanced by that etching process, and thus the hole 13 becomes larger. This may cause a short-circuit with the peripheral conductive layer and an increase in the coupling capacitance. When the side etching of the hole 13 is excessive, the resist film 12 will come off from the second insulation layer 11 and the hole 13 can not be formed in a predetermined shape. Further, there are some cases where the second poly-Si layer 10 also becomes etched.
In order to improve this situation, the prior art device of FIG. 3 was designed. This device is basically formed using the same process as that of the device of FIGS. 1 and 2. The difference is that the holes 16 and 17 are first formed in the first insulation layer by photo-engraving. By that process, the insulation layer 9 on the first conductive layer 8 and on the N.sup.+ region 4 where a hole is to be formed in a later process is only the second insulation layer 11, and the thickness of this layer is thus the same as that of the insulation layer on the second poly-Si layer 10. Thus each hole can be formed as designed and excessive margins with the peripheral conductive portions need not be prepared because only the second insulation layer 11 is etched by the photo-engraving process.
But this process requires additional steps in forming the hole in the first insulation layer 9, thus lowering production efficiency.
The prior art device of FIG. 4 has the same faults as that of the above-discussed device, also. In this device, the conductive layers 8 and 8' on the separating layer 5 are formed first and next the second conductive layer 10 is formed. Then the contact holes to the first conductive layer 8 and to the N.sup.+ region 4 are formed. In this case, as the depth t.sub.4 of the insulation layer on the first conductive layer 8 is larger than the depth t.sub.5 of the insulation layer on the N.sup.+ region 4, the hole on the N.sup.+ region 4 will be formed too large. So the N.sup.+ region 4 must be formed beforehand with much surplus. Further, excessive etching may cause separation of the resist film 12 and erosion of the N.sup.+ region 4.